The present invention relates generally to a non-volatile semiconductor memory device. More particularly, the present invention relates to a non-volatile semiconductor memory device which makes it possible to store four-value information (two-bit information) in one memory cell and increases a memory capacity. The present invention relates to a technology which will be useful when applied to an electrically rewritable non-volatile semiconductor memory device such as a flash memory. A conventional non-volatile semiconductor memory device capable of storing information by injecting an electron into a floating gate, such as a flash memory, is described, for example, in “1994 Symposium on VLSI Circuits Digest of Technical Papers”, pp. 61-62. Each of the (1) erase, (2) write, (3) write verify and (4) read operations of this conventional flash memory will be explained.
FIG. 35 of the accompanying drawings shows a principal circuit portion of memory cells MC connected to a word line WL and a bit line EL so as to explain the operations of a flash memory for storing two-value information (one-bit information) in one memory cell.
Reference numerals N9 to N12 denote NMOS transistors for executing a switch operation (hereinafter merely called the “NMOS switch”). A source line is represented by symbol SOL.
The state where electrons are injected to the floating gate of the memory cell MC and the threshold voltage of this memory cell MC (Vth0) is high will be assumed as the erase state, that is, the state where the written information is “0”. On the contrary, the state where the electron is not injected into the floating gate and the threshold voltage of the memory cell MC is low (Vth1) will be assumed as a written state, that is, the state where the written information is “1”.
FIG. 36 typically shows a threshold voltage distribution of the memory cell when the memory cell latches the two-value information in this way.
(1) Erase Operation:
In this example, the erase operation is made for each word line. The erase operation is carried out by setting the word line WL to 12 V, for example, and applying −4 V, for example, to a substrate voltage VWEL of the memory cell MC and a source line SOL. In consequence, the electrons are injected to the floating gate, the threshold voltage of the memory cell MC becomes high, and the erase state is established.
(2) Write Operation:
The write operation is the one that extracts the electrons in the floating gate and lowers the threshold voltage of the memory cell.
First, an input/output line IO is set to a high level (called also “High”) when write is made to the memory cell MC and to a low level (called also “Low”) when write is not made, and a sense latch SL is caused to latch the data of the “High” or “Low” level.
Next, the operation power source voltage VSA of the sense latch SL is raised to 4 V, for example, from the power supply voltage VCC to turn ON the NMOS switch N10. If “High” is latched by the sense latch SL at this time, the node side A of the sense latch SL is “High”, so that the NMOS switch N11 is turned ON and the bit line BL is precharged to 4 V through the NMOS switches N10 and N11. If “Low” is latched by the sense latch SL, on the other hand, the node A is “Low”, so that the NMOS switch N11 is OFF and the bit line BL is not precharged and falls to 0 V. Thereafter, the voltage of a control signal line PG is lowered to turn OFF the NMOS switch N10, and the control signal line TR is then raised to turn ON the NMOS switch N12. The word line WL is set to −9 V, for example, and the write operation is carried out. At this time, the source line and the substrate voltage VWEL of the memory cell MC are kept at 0 V. The voltage of the control signal line TR is then lowered to turn OFF the NMOS switch N10 to set the word line WL to 0 V, the control signal line DDC is raised to turn ON the NMOS switch N9 and to discharge the bit line BL. The voltage of the control signal line DDC is lowered to turn OFF the NMOS switch N9, and the next write verify operation is carried out.
(3) Write Verify Operation:
In the write verify operation, the voltage VSA is first set to 1 V, for example, to raise the control signal line PG and turn ON the NMOS switch N10. As described in the (2) write operation, if “High” is latched in the sense latch SL, the NMOS switch N11 is turned ON, and the bit line BL is precharged to 1 V. If “Low” is latched, the NMOS switch N11 is turned OFF, so that the bit line BL is not precharged. Next, the voltage of the control signal line PG is lowered to turn OFF the NMOS switch N10. If the word line WL is 1.5 V, and the source line and the substrate voltage VWEL of the memory cell MC are 0 V, for example, the memory cell MC is turned ON if its threshold voltage is low, a current flows from the bit line BL to the source line side and hence, the potential of the bit line BL drops, due to the (2) write operation. If the threshold voltage of the memory cell MC is not under the low state by the (2) write operation, on the other hand, the memory cell MC is not turned ON and the potential of the bit line BL does not drop.
After the voltage of the word line is returned to 0 V, the control signal line TR is raised to turn ON the NMOS switch N12, If the potential of the bit line BL lowers at this time, the potential of the node A lowers, too, and “High” latched by the sense latch SL inverts to “Low”. If the potential of the bit line BL does not lower, however, the potential of the node A does not lower and “High” latched by the sense latch SL remains “High” and does not lower.
When the (2) write operation is made to the memory cell MC and the threshold voltage of the memory cell MC lowers (the state where “1” is written), “High” latched by the sense latch SL inverts to “Low” due to the write verify operation and the write operation is judged as being finished. In contrast, when the threshold voltage of the memory cell MC remains high due to the (2) write operation (the state where “0” is written), the operations (2) and (3) are repeated until the sense latch SL inverts from “High” to “Low”.
(4) Read Operation:
First, the control signal line DDC is raised to turn ON the NMOS switch N9 and the bit line BL is discharged. Next, the voltage VSA is set to 1 V, for example, to raise the control signal line SET and to turn ON the NMOS switch N13. The node side A of the sense latch circuit SL is set to 1 V and the control signal line TR is raised. The NMOS switch N12 is turned ON and the bit line BL is precharged to 1 V. The voltage of the control signal line TR is lowered, the NMOS switch N12 is turned OFF, the voltage of the SET line is lowered and the NMOS switch N13 is turned OFF. The substrate voltage VWEL and the voltage of the source line are then set to 0 V, for example, and the word line WL is set to the power supply voltage VCC. When the threshold voltage of the memory cell MC is low, the memory cell MC is turned ON, a current flows from the bit line BL to the source line side and the potential of the bit line BL drops. When the threshold voltage of the memory cell MC is high, the memory cell MC is not turned ON and the potential of the bit line BL does not drop. Next, after the voltage of the word line WL is set to 0 V, the control signal line TR is raised and the NMOS switch N12 is turned ON. If the memory cell MC is turned ON, the potential of the bit line BL is low. Therefore, the potential of the node A is low, too. If the memory cell MC is not turned ON, on the other hand, the potential of the bit line BL does not drop, and the potential of the node A does not drop, either. In this way, the information stored in the memory cell MC, that is, the information corresponding to the case where the threshold voltage is low (the state where “1” is written) and the case where it is high (the state where “0” is written), is read out.
A greater memory capacity and a smaller area have been desired for non-volatile semiconductor memory devices. As described above, however, when only one-bit information can be stored in one memory cell, the number of memory cell arrays must be increased to achieve a greater capacity. For this reason, in order to achieve a greater capacity in the non-volatile semiconductor memory devices, the chip area must be inevitably increased irrespective of the progress of the micro fabrication technology in the technical field of the semiconductor integrated circuits.